1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and, more particularly, to a manufacturing method of a semiconductor device in which a dummy pillar for extending a gate electrode of a transistor in the lateral direction is formed of a silicon oxide film.
2. Description of Related Art
The chip size of a semiconductor device, especially, that of a memory device is reduced year by year for cost reduction. Accordingly, in a DRAM (Dynamic Random Access Memory), a vertical type transistor having a 4F2 structure is now being adopted as a cell transistor. Regarding a transistor for peripheral circuit, since requirements for size reduction are not stringent than in the case of the cell transistor, a conventional planar type transistor is still continuously being adopted. However, in the case where the transistor structure differs in the cell and peripheral circuit, the number of processes significantly increases. Thus, recently, adoption of a vertical type transistor having a 4F2 structure also as the transistor for peripheral circuit is under consideration (refer to Japanese Patent Application Laid-Open No. 2008-288391).
As disclosed in Japanese Patent Application Laid-Open No. 2008-288391, in the vertical type transistor installed in a peripheral circuit, two adjacent silicon pillars (first and second silicon pillars) are used. The first silicon pillar is used as a channel. Impurity diffusion layers are formed respectively at the upper and lower portions of the first silicon pillar. The side surface of the first silicon pillar is covered by a gate electrode through a gate insulating film. The second silicon pillar is a dummy pillar used for extending the length of the gate electrode in the lateral direction, and a gate contact plug is provided in the extended portion.
In recent years, a technique that forms a dummy pillar using an insulating film such as a silicon oxide film is proposed. This technique aims to prevent short circuit between a silicon substrate and a gate contact plug and functions well in this regard. However, this technique has a high probability of occurrence of gate electrode disconnection.
This will be explained more concretely taking a case where the dummy pillar is formed of a silicon oxide film as an example. A process for processing a silicon pillar for a channel as a transistor includes a process of intentionally or incidentally eroding the silicon oxide film, such as wet etching and acid washing with phosphoric acid or hydrofluoric acid. In the case where the dummy pillar is formed of the silicon oxide film, the dummy pillar is eroded through the above process. As a result, the diameter of the dummy pillar is reduced to increase the distance between the surface of the silicon pillar and the surface of the dummy pillar, resulting in insufficient integration of gate electrodes covering the side surfaces of the silicon pillar and the dummy pillar.